For digital verification engineers

Learn SystemVerilog, UVM, and DV methodology

Learn digital verification (DV) fundamentals through worked examples and hands-on quizzes, with instant feedback as you go.

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Learning paths

SystemVerilog Basics

Data types, procedural blocks, interfaces, and assertions.

16 lessons

UVM Basics

UVM components, TLM communication, sequences, and the factory mechanism.

10 lessons

Advanced UVM

Multi-agent coordination, virtual sequences, and the register abstraction layer (RAL).

6 lessons

DV Methodology

Practical verification wisdom: test-planning mindset, coverage-driven judgment, and debugging intuition.

15 lessons

Advanced SVA

Sequences and properties in depth: implication operators, protocol-compliance assertions, and bind.

7 lessons