All tutorials

Data types, procedural blocks, interfaces, and assertions.

• 01Why SystemVerilog? From Verilog to a Verification Language→
• 02Basic Syntax: Modules, Literals, and Printing→
• 03Running Your First Simulation: EDA Playground, Waveforms, and $finish→
• 04Data types: the difference between logic, reg, and wire→
• 05More Data Types: 2-State vs. 4-State, enum, struct, and typedef→
• 06Arrays: Packed vs. Unpacked, Dynamic Arrays, Associative Arrays, and Queues→
• 07Operators and Procedural Statements→
• 08Always Blocks and Processes: initial, always_comb, always_ff, always_latch→
• 09Tasks and Functions: Reusable Behavior in SystemVerilog→
• 10Introduction to OOP: Classes and Objects in SystemVerilog→
• 11OOP Continued: Inheritance, Polymorphism, and Virtual Methods→
• 12Randomization and Constraints: rand, randc, and constraint Blocks→
• 13Interfaces and Modports: Bundling and Organizing Signals→
• 14Processes and Interprocess Communication: fork-join, Events, Semaphores, and Mailboxes→
• 15Assertions: Immediate and Concurrent Assertions (SVA Basics)→
• 16Packages, Scope, and a Small Testbench Capstone→

UVM components, TLM communication, sequences, and the factory mechanism.

• 01Introduction to UVM: what problem does it actually solve?→
• 02The UVM Component Tree and Phasing→
• 03Build and Run Your First UVM Test→
• 04uvm_object and Transactions→
• 05config_db and Virtual Interface Handoff→
• 06The Factory: Registration, create(), and Overrides→
• 07Sequences and Sequencers→
• 08Driver and Monitor: TLM Ports in Practice→
• 09Scoreboard and Analysis Ports→
• 10Capstone: Assembling a Complete UVM Environment→

Multi-agent coordination, virtual sequences, and the register abstraction layer (RAL).

• 01Meet AXI4-Lite and axil_regfile→
• 02AXI4-Lite Driver, Monitor, and Agent→
• 03A Second Interface: irq Monitor and Multi-Agent Environments→
• 04Virtual Sequencer and Virtual Sequences→
• 05UVM RAL: the Register Abstraction Layer→
• 06Capstone: Assembling the Advanced Environment→

Practical verification wisdom: test-planning mindset, coverage-driven judgment, and debugging intuition.

• 01Coverage in One Page: Functional vs. Code Coverage→
• 02Functional Coverage in Depth: bins, Crosses, and Options→
• 03Code Coverage: Line and Branch→
• 04Code Coverage: Toggle→
• 05Code Coverage: FSM→
• 06Coverage-Driven Verification: Closing the Loop→
• 07What a Test Plan Is, and Why It Comes First→
• 08From Spec to Feature List→
• 09The Scenario Taxonomy: Legal, Boundary, Illegal, Concurrent→
• 10Risk-Based Prioritization: What to Write First→
• 11The Test Plan as a Living, Traceable Document→
• 12Where a Failure Lives: Four Places to Check First→
• 13Reading the Failure Signature→
• 14The Diagnostic Method: Isolate, Instrument, Hypothesize, Confirm→
• 15Writing the Bug Down, and Closing the Loop→

Sequences and properties in depth: implication operators, protocol-compliance assertions, and bind.

• 01Beyond |-> and ##[m:n]: Where This Track Picks Up→
• 02Why Assertions, Not If-Statements: The Case for SVA→
• 03Sequence Operators in Depth→
• 04Properties and Implication→
• 05Protocol-Compliance Assertions: Checking What Was Never Tested→
• 06bind: Checking a DUT Without Modifying It→
• 07Assertion Coverage, and Closing Back to Coverage→