SystemVerilog Basics

Data types, procedural blocks, interfaces, and assertions.

1. 01Why SystemVerilog? From Verilog to a Verification LanguageUnderstand the core difference between describing hardware and executing software, where plain Verilog falls short for verification, what SystemVerilog actually adds, and the design-vs-verification-code mental model that runs through this whole series.
2. 02Basic Syntax: Modules, Literals, and PrintingLearn to read and write a module's declaration and instantiation, SystemVerilog's numeric literal format, $display/$sformatf and message severity levels, parameter/localparam module configuration, and the ternary (conditional) operator — the connective tissue every later chapter's examples assume you already know.
3. 03Running Your First Simulation: EDA Playground, Waveforms, and $finishActually run a SystemVerilog testbench: set up EDA Playground, understand $timescale and its more modern replacement, timeunit/timeprecision, learn why simulation never ends without $finish, dump and read a waveform with $dumpfile/$dumpvars, and get a complete, copy-pasteable example that works end to end.
4. 04Data types: the difference between logic, reg, and wireUnderstand how SystemVerilog's logic type unifies and simplifies Verilog's reg/wire split, across both combinational and sequential logic, plus where each type's boundaries still apply.
5. 05More Data Types: 2-State vs. 4-State, enum, struct, and typedefUnderstand the difference between 2-state and 4-state data types and when to use each, name states with enum, bundle related fields with struct, and give types meaningful names with typedef.
6. 06Arrays: Packed vs. Unpacked, Dynamic Arrays, Associative Arrays, and QueuesMeet SystemVerilog's array family: the difference between packed and unpacked arrays, dynamic arrays whose size is only known at runtime, associative arrays indexed by an arbitrary key, and queues that can grow and shrink, plus when to reach for each.
7. 07Operators and Procedural StatementsA quick pass over the parts of if/case/loops you already know from general programming, spending the real time on what's actually new in SystemVerilog: repeat/forever loops, unique/priority case, bitwise vs. logical operators, 4-state case equality ===/!==, increment/decrement operators, and streaming operators.
8. 08Always Blocks and Processes: initial, always_comb, always_ff, always_latchA systematic look at what initial, plain always, always_comb, always_ff, and always_latch are each for — and finally deliver on earlier chapters' promise to fully explain the difference between blocking (=) and non-blocking (<=) assignment.
9. 09Tasks and Functions: Reusable Behavior in SystemVerilogSort out the real difference between function and task, passing arguments by value vs. by reference (ref), default argument values, void functions, and a genuinely easy mistake to make: automatic vs. static lifetime.
10. 10Introduction to OOP: Classes and Objects in SystemVerilogMap what you already know about classes and objects onto SystemVerilog's specific syntax, focusing on one key point that's completely different from struct: an object is a handle (reference), not a value; then learn to write a copy() method, restrict access with local/protected, share data across objects with static members, and parameterize a class with #(type T).
11. 11OOP Continued: Inheritance, Polymorphism, and Virtual MethodsBuild inheritance relationships with extends, understand why polymorphism doesn't work the way you'd expect without the virtual keyword, learn to safely convert a base-class handle back to a subclass handle with $cast, and see how this sets up the factory mechanism in the next track, UVM.
12. 12Randomization and Constraints: rand, randc, and constraint BlocksLearn to declare randomizable properties with rand/randc, describe rules with constraint blocks, call randomize() and check its result, use $urandom/$urandom_range and std::randomize() for randomization outside a class, and control what gets randomized at runtime with rand_mode and constraint_mode — the core mechanism verification code uses to generate stimulus.
13. 13Interfaces and Modports: Bundling and Organizing SignalsUnderstand why interface exists for connecting a DUT to a testbench, how modport restricts each side's read/write direction over the signals so tools catch connection mistakes at compile time, and how a clocking block gives a sequential DUT's signals a precise, race-free timing contract.
14. 14Processes and Interprocess Communication: fork-join, Events, Semaphores, and MailboxesLaunch concurrent processes explicitly with the three fork-join variants, clean up background processes with disable fork/wait fork, then coordinate them with event, semaphore, and mailbox — synchronizing, limiting resource access, and passing data between processes, the concurrency foundation real testbenches are built on.
15. 15Assertions: Immediate and Concurrent Assertions (SVA Basics)Declare conditions to check with assert instead of hand-writing if/$error, then learn property and sequence for describing relationships across multiple clock cycles — the basics of SystemVerilog Assertions (SVA), stopping short of full formal verification.
16. 16Packages, Scope, and a Small Testbench CapstoneLearn to organize code across files and avoid naming collisions with package, then assemble fifteen chapters' worth of building blocks — interfaces, classes, randomization, mailboxes, tasks, fork-join, and assertions — into one small testbench that actually runs, and see what trouble hand-writing all of this runs into at scale.